1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a mask read only memory (ROM).
2. Description of the Related Art
A mask ROM is a device for programming a desired cell transistor by selectively implanting impurity ions into a channel region of the cell transistor in the course of fabricating the same. Once information is programmed, the information cannot be erased. It is difficult to attain a high density of integration in a NOR-type mask ROM relative to a NAND-type mask ROM. Accordingly, to increase the integration density of the NOR-type mask ROM, a multi-bit cell mask ROM has been developed. The multi-bit cell mask ROM reads out information stored in the respective cell transistors by successively applying a multitude of different voltages, e.g., three different voltages, to a word line functioning as a gate electrode of a cell transistor. For example, the information of a selected cell transistor is read out by successively applying a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage to a word line connected to the selected cell transistor having a predetermined threshold voltage. Here, if the predetermined threshold voltage is lower than the first voltage, the multi-bit cell mask ROM outputs a signal having 2-bit information "00". If the predetermined threshold voltage is higher than the first voltage and lower than the second voltage, the multi-bit cell mask ROM outputs a signal having 2-bit information "01". If the predetermined threshold voltage is higher than the second voltage and lower than the third voltage, the multi-bit cell mask ROM outputs a signal having 2-bit information "10". If the predetermined threshold voltage is higher than the third voltage, the multi-bit cell mask ROM outputs a signal having 2-bit information "11".
As described above, in a multi-bit cell mask ROM a cell transistor must be programmed so as to have a threshold voltage belonging to one of four voltage ranges. The voltage ranges are divided into first through fourth voltage ranges. Accordingly, the multi-bit cell mask ROM must adjust the threshold voltage of a cell transistor more accurately and uniformly than a conventional mask ROM. As a result, a high level of uniformity is required during impurity ion implantation process.
FIG. 1 is an equivalent circuit diagram of a pair of strings sharing a bit line in a cell array portion of a general NOR-type mask ROM. FIG. 2 is a plan view illustrating cell array portions spaced a predetermined distance apart from each other on which a pair of strings are two-dimensionally arranged, according to the equivalent circuit diagram of FIG. 1.
Referring to FIGS. 1 and 2, a bit line B/L is connected to a string select controller SSC, which is connected to two drain lines D1 and D2. The SSC selects one of a pair of drain lines D1 and D2 responsive to a voltage applied to first and second string select lines SSL1 and SSL2. A plurality of cell transistors are connected in parallel to the first drain line D1, the plurality of cell transistors constituting a first string. The plurality of cell transistors share a first source line S1. Likewise, a plurality of cell transistors are connected in parallel to the second drain line D2, the plurality of cell transistors constituting a second string. The plurality of cell transistors share a second source line S2. The pair of the drains lines D1 and D2 and the pair of the source lines S1 and S2 are arranged on the surface of a semiconductor substrate parallel to each other. The drain lines D1 and D2 and the source lines S1 and S2 are impurity layers doped with impurities of a conductivity type different from that of the semiconductor substrate. A plurality of word lines W/L1, . . . W/Ln are arranged across the pair of the drains lines D1 and D2 and the pair of the source lines S1 and S2. The distance d (FIG. 2) between the word lines becomes narrower with increased integration of a mask ROM. Generally, the distance (d) between the word lines has a value corresponding to a minimum design rule.
In FIG. 2, a portion showing the first through third word lines W/L1, W/L2 and W/L3 is a first region (a) representing a part of a pair of strings sharing one bit line. A portion showing another word lines W/L1' and W/L2' is a second region (b) representing a part of a pair of strings sharing another bit line (not shown). Thus, there are also provided a pair of drain lines D1' and D2' and a pair of source lines S1' and S2' in the second region (b). Also, patterns M1 and M2 indicated by a dotted line are patterns for an ion implantation mask for programming a desired cell transistor by selectively implanting impurity into a channel region of the cell transistor. Here, the ion implantation mask pattern M1 corresponds to a mask pattern for programming a cell transistor P shown in FIG. 1.
FIGS. 3 through 6 are cross-sectional views illustrating a method for fabricating a conventional NOR-type mask ROM, taken along the line BB, shown in FIG. 2. Here, portions indicated by reference symbols (a) and (b) correspond to the first and second regions shown in FIG. 2, respectively.
Referring to FIG. 3, a plurality of parallel drain lines (D1, D2, D1' and D2' of FIGS. 1 and 2) and a plurality of source lines (S1, S2, S1' and S2' of FIGS. 1 and 2) are formed on a predetermined area of a semiconductor substrate 1 by implanting an impurity having a conductivity type different from that of the semiconductor substrate 1. A gate oxide layer 3, a conductive layer 5, an anti-reflective layer 7, and a hard mask oxide layer 9 are formed over the entire surface of the semiconductor substrate 1 where the plurality of drain lines and the plurality of source lines are formed. The conductive layer 5 is formed of a tungsten polycide layer having a resistivity lower than the doped polysilicon layer, and the hard mask oxide layer 9 is formed of a Chemical Vapor Deposition (CVD) oxide layer. The anti-reflective layer 7 is formed of a silicon oxynitride layer.
Referring to FIG. 4, an oxide layer pattern 9a is formed by patterning the hard mask oxide layer 9 using a photolithography/etching process. The anti-reflective layer 7 and the conductive layer 5 are sequentially etched using the oxide layer pattern 9a as an etching mask thereby forming a plurality of word lines W/L1, W/L2, W/L3, W/L1' and W/L2' and an anti-reflective layer pattern 7a positioned thereon. Subsequently, an insulator layer 11, e.g., a CVD oxide layer having an excellent step coverage, is formed over the entire surface of the semiconductor substrate where the plurality of word lines are formed.
Referring to FIG. 5, the insulator layer 11 is anisotropically etched to form a spacer 11a at the side walls of the respective word lines W/L1, W/L2, W/L3, W/L1' and W/L2'. As shown in FIG. 5, the thickness of a material layer remaining on the word lines in the first region (a) is different from that of a material layer remaining on the word lines in the second region (b). In other words, whereas only a modified anti-reflective layer pattern 7a' remains on the word lines in the first region (a), a modified oxide layer pattern 9a' and the anti-reflective layer pattern 7a remain on the word lines in the second region (b). This is because all etching processes including one for forming the spacer 11a do not show uniform etching rates throughout the semiconductor substrate 1. Here, anisotropic overetching for forming the spacer 11a may be carried out to expose all the word lines. However, in such a case, etching damage applied to the surface of the semiconductor substrate 1 may be severe enough to cause a leakage current in a cell transistor. Thus, it is not easy to carry out anisotropic overetching.
Referring to FIG. 6, a photoresist layer is formed over the entire surface of the semiconductor substrate where the spacer 11a is formed. The photoresist layer is patterned using a photomask on which ion implantation mask patterns M1 and M2 shown in FIG. 2 are formed. Doing so forms a photoresist pattern 13 opening a cell transistor having a predetermined region of the first word line W/L1 in the first region (a) as a gate electrode and another cell transistor having a predetermined region of the word line W/L1' in the second region (b) as a gate electrode. Subsequently, an impurity is implanted into the channel region of the opened cell transistors using the photoresist pattern 13 as an ion implantation mask to form impurity layers 15a and 15b. At this time, the impurity layer 15a formed in the first region (a) and the impurity layer 15b formed in the second region (b) have different depth and concentration. This is because the thickness of a material layer remaining on the word lines in the first region (a) is different from that of a material layer remaining on the word lines in the second region (b), as shown in FIG. 5. As a result, threshold voltages of cell transistors programmed in one semiconductor substrate are different according to their positions.
Since threshold voltages of cell transistors programmed in one semiconductor substrate are different according to their positions, errors may be generated during a read operation. In particular, in a multi-bit cell mask ROM, the threshold voltage of a programmed cell transistor must be uniformly adjusted to prevent reading errors from being generated.
Accordingly, a need remains for a method for fabricating a mask ROM that prevents differences in the threshold voltages of programmed cell transistors.